RISCV SOC

We are working on a RISCV Soc design whose peripheral list has "everything including the kitchen sink". The goal is to have a proven reference design and the ecosystem around it and enable our clients to build their chip on a proven platform and achive rapid time to market.

RISCV SOC

Dyumnin’s RISCV SOC is built around a 64bit Quad core server class RISCV CPU. The chip has one or more of the following subsystems.

  1. AI/ML subsystem
  2. Automotive subsystem
  3. Multimedia Subsystem
  4. Memory subsystem
  5. Cryptographic subsystem
  6. Communication subsystem.

The testchip will be available as an FPGA for evaluation and testing.

Each subsystem has one or more of the associated IP’s. And based on the enduser requirement a new SOC can be spun with the custom peripherals required by the enduser application.

Core SoC

The core SOC consists of a Quad code server class RISCV CPU with the other components required for a functional CPU subsystem. In future it will be possible to replace this subsystem with a custom core.

AI Acclerators.

The AI accelerator system consists of a custom CPU tightly coupled with a tensor flow unit for accelerating common AI operations.

Multimedia Subsystem

The multimedia subsystem contains IP for

  1. HDMI,
  2. Display Port,
  3. MIPI,
  4. Camera Subsystem,
  5. Gfx accelerators and
  6. Digital Audio.

Memory Subsystem

This consists of the IP’s required to connect to most of the memory chips and modules available in the market. This includes

  1. DDR,
  2. MMC,
  3. ONFI,
  4. NorFlash,
  5. SD/SDIO protocols.

Communication subsystem

The communication subsystem supports most of the protocols used to connect between devices e.g.

  1. PCIe,
  2. Ethernet,
  3. USB,
  4. SPI,
  5. I2C,
  6. UART etc.

Automotive subsystem

CAN, CAN-FD and SafeSPI IP’s are available to connect to automotive systems.

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